In the design of a processing system including, for example, a digital signal processor (DSP) chip, it may be beneficial to have access to functionality, computing power and/or specialized tasks not implemented on the DSP chip. For example, the DSP may be a wireless baseband intended to support various standards for wireless communications. However, the baseband platform may need to be modified to add support for new and/or different standards. For example, in the wireless context, a baseband processor may need to support global system for mobile communications (GSM), enhanced data GSM environment (EDGE), time division multiple access (TDMA), wideband TDMA, general packet radio service (GPRS), and other standards, and may need to be modified to support, for example, TDSCMA, other third generation (3G) standards, or standards to be developed in the future.
The additional hardware needed to extend the baseband processor to support one standard may not be necessary to support another standard, or may not be mature enough to merit incorporation into the baseband architecture. To address this, specialized hardware to support a particular standard and/or specific accelerators or optimizations not available on the baseband processor may be implemented on an external coprocessor (e.g., a coprocessor provided external to the baseband chip). As new standards or capabilities arise, a specialized coprocessor may be designed to implement the desired functionality without requiring specialized modifications and/or additions to the DSP itself (i.e., without modifying the core DSP integrated on the chip).
In addition, it may benefit a particular processing application for the DSP to be capable of utilizing other functionality that is not resident on the DSP chip. For example, various hardware accelerators, specialized filtering components, noise reduction algorithms, and other signal processing capabilities may benefit the DSP, which itself does not implement the specific functionality desired. Accordingly, various design situations may benefit from a system architecture having a DSP capable of communicating with an external coprocessor in order to take advantage of the functionality provided by the external coprocessor.
To interface between a DSP and a coprocessor, information must be transferred from a bus internal to the DSP to a bus internal to the coprocessor. That is, data must typically be transferred and obtained from off-chip. Numerous bus interface standards exist, such as Universal Serial Bus (USB), PCI Express, PCI-X, RapidIO, etc., establishing various protocols for serial and parallel bus transfers. However, these standards were developed with particular design considerations and having specific goals and priorities, and therefore may be unsuitable for the interfacing between a DSP and a coprocessor.